1. Field of the Invention
The present invention relates in general to ferroelectric memories and in particular to such memories that include memory cells including ferroelectric capacitors and arranged in rows and columns to form an array.
2. Statement of the Problem
It is well known that ferroelectric materials are capable of retaining a polarization which can be used to store information in a non-volatile memory. For example, if a strong enough electric field or voltage is placed across a ferroelectric capacitor, when the voltage is removed, a polarization in the direction of the field remains. If the field is then placed across the same capacitor in the opposite direction, the ferroelectric material switches, and when the field is removed, a polarization in the opposite direction remains. Electronic circuits have been designed to associate the polarization in one direction with a digital logic “1” state, and polarization in the opposite direction with a logic “0” state. See, for example, the circuits described in U.S. Pat. No. 2,876,436 issued Mar. 3, 1959 to J. R. Anderson. Like other integrated circuit memories, these circuits include memory cells arranged in rows and columns, each memory cell including at least one switch, a capacitor having a pair of electrodes, and the memory also including plate lines, sometimes referred to as drive lines, connected to one electrode of the capacitor in each cell, and bit lines connected to the other electrode of the capacitor through the switch. In this disclosure, we shall refer to the “plate” line as a “drive” line, as is sometimes done in the art. In the Anderson patent cited above, the switch is a diode. As is known in the art, the switch can be a transistor having a gate, a source and a drain, and the memory includes word lines connected to the control gate of the transistor. See, for example, U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 to S. Sheffield Eaton, Jr. The transistor acts as a switch controlled by its gate to connect the capacitor to the bit line. Information is written into a-memory cell by placing either a high or a low voltage on the bit line, turning the transistor on to connect the bit line to the capacitor, and placing a predetermined voltage between the high and low voltage on the drive line. The high voltage causes the memory cell to assume one polarization state, and the low voltage causes the memory cell to assume the opposite polarization state. The, memory cell is read by creating a voltage difference between the bit line and drive line, and connecting the bit line to the capacitor via the transistor. If the ferroelectric state changes due to the applied voltage, the bit line will assume a first voltage, and if the ferroelectric state does not switch, then the bit line will assume a second voltage. The bit line voltage is compared to a reference voltage that is about half-way between the first and second voltages; if the bit line voltage is below the reference voltage, a sense amp drives an output low, and if the bit line voltage is above the reference voltage, a sense amp drives an output high. In this way, the state of the ferroelectric capacitor prior to reading determines the output state when the cell is read.
In the above-described memory and other similar conventional ferroelectric memories, the drive line is pulsed. The drive line, being relatively long and connected to the electrodes of many capacitors, has a high capacitance. Thus, it takes a relatively long time for the voltage to rise to its full value, with the result that the time to read and write to the memory is long. To speed up the read and write processes, ferroelectric memories in which the drive line is not pulsed have been developed. See Hiroki Koike et al., “A 60-ns 1-Mb Nonvolatile Ferroelectric Memory With A Nondriven Cell Plate Line Write/Read Scheme, IEEE Journal of Solid State Circuits, Vol. 31, No. 11, November 1996. Another solution has been to make the drive line parallel to the bit line, so that only one capacitor at a time is pulsed. See the embodiment of FIG. 6 in the Eaton, Jr. patent mentioned above. Segmented drive lines have also been proposed to speed up the drive line cycle and reduce power. See U.S. Pat. No. 5,598,366 issued, Jan. 28, 1997 to Kraus et al. However, all these memories have not been successful due to significant disturb problems. “Disturb” is a problematic feature of most prior art ferroelectric memories in which “disturb” voltages, usually small in amplitude, are unavoidably applied to non-accessed memory cells., which voltages can change the memory state and thus lead to erroneous-readings. For example, in the Koike et al. reference, it is explained that leakage from the bit line and drive line to the nodes of a capacitor that is not accessed can destroy the data. This problem is overcome with a compensation scheme which adds complexity to the memory and slows it down. Thus, the disturb problem has either resulted in memories that have been made more complex and slower to overcome the disturb, as in the Koike et al. reference, or simply have resulted in the design being too unreliable to be successful, such as the Eaton, Jr. patent. Moreover, the average power requirements of such cells remains quite high.
Up until recently, all ferroelectric materials tended to fatigue overtime,-and the switching charge decreased to a point where the cell could no longer be read. About ten years ago, a class of materials, called layered superlattice compounds herein, had been discovered that do not fatigue. However, while the switching charge remains relatively stable in these materials, the materials still age, i.e., the magnitude of the first and second voltages generally depends on the history of the memory cell. For example, depending on the history, both the first and second voltages in one reading on a specific cell will differ by some voltage factor from the first and second voltages of a later reading of the same cell; or the hysteresis curve may drift overtime in the order of milliseconds due to redistribution of charge within the capacitor. Thus, while the reference voltage will be between the first and second voltages for one reading, in a later reading both the first and second voltages may be above the reference voltage. This generally results in a misreading of the memory cell. Thus, these memories are not “safe” in that the reading or sensing of the data is relatively unreliable.
A typical solution to the above problems is disclosed in U.S. Pat. No. 4,888,733 issued Dec. 19, 1989 to Kenneth J. Mobley. The memory disclosed in the Mobley patent isolates the ferroelectric capacitor with two transistors, which avoids the disturb problem. It also pulses the ferroelectric capacitor in one direction and stores the developed charge on a first temporary storage capacitor, pulses the ferroelectric capacitor in the opposite direction and stores the developed charge on a second temporary storage capacitor, and then compares the stored charges on the two storage capacitors. Thus, this memory essentially compares two states of the same capacitor taken one after another in a time interval that is too short for aging or other changes to take place, which avoids the aging problem. However, this solution triples the length of time it takes to read a memory; thus, this memory is not competitive with state-of-the-art memories which require fast read times. Further, the extra temporary storage capacitors are linear capacitors, which take up significant additional room in the memory, so a memory according to the Mobley design is relatively bulky and is not competitive in a memory market where memory chips are increasingly dense. There are many other multi-capacitor/multi-transistor ferroelectric memories that have been proposed to solve the above problems, some of which have been incorporated into commercial products. All of them are both several times more dense and slower than conventional DRAMs.
The above problems, particularly the aging problem and the “disturb” problem, are most severe in the fastest and densest memory architectures. Thus, commercial applications of ferroelectric memories up to now have been limited to relatively slow and bulky architectures, such as the Mobley design. It would be highly desirable to have a ferroelectric memory architecture that was faster and less bulky than the Mobley design, yet was not subject to the problem of disturb. Such a memory design that also avoided the aging problem would be a significant advance in the art.